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TPMC630 Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O 
 
User configurable Xilinx FPGA with 300,000 (TPMC630-1x) or 600,000 (TPMC630-2x) system gates; Flash device in-system programmable; 32 bit PCI target interface by PLX PCI9030; FPGA clock options: Local clock oscillator / PLL programmable clock generator (200 KHz - 166 MHz), 6 clock outputs connected to FPGA; I/O lines: 64 TTL I/O (TPMC630-x0x), 32 differential I/O (TPMC630-x1x) or 32 TTL I/O and 16 differential I/O (TPMC630-x2x) / TTL signaling voltage (maximum current: +/-24 mA) or EIA-422/-485 signaling level / direction individually programmable; I/O access: 64 I/O lines on HD68 front connector, parallel to up to 64 I/O lines on rear connector P14; Operating temperature: -40°C to +85°C
 TPMC630 Data Sheet
 TPMC630-DOC User Manual for TPMC630
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新 北 市 汐 止 區 康 寧 街 169 巷 23 號 7 樓 之 一

公司電話:+886-2-2695-8906(代表號)

 02-2695-6755, 02-2695-7011, 02-2695-7033

公司傳真:+886-2-26958911

顏永富 分機35 johnny@bentech-taiwan.com

上次更新日期: 2016年04月13日。