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TIP630 Reconfigurable FPGA with 48 TTL I/O 
User configurable FPGA with 200,000 system gates; 48 digital I/O lines individually programmable as input, output, tri-state I/O; 6 pull up resistor networks (selectable pull up voltage +3.3V or 5V), ESD and overvoltage protection for each I/O line; Xilinx XC2S200-5 SpartanII FPGA logic configurable via IP bus or optional by PROM XC17S200APD8I; FPGA clock options: IP bus clock (8 or 32 MHz) / Local 32 MHz clock oscillator / PLL programmable clock generator CY22150 (250 KHz -166 MHz), 2 clock outputs connected to FPGA; Operating temperature -40°C to +85°C
TIP630 Data Sheet
TIP630-DOC User Manual for TIP630
TIP630-SW-42 VxWorks Software Support for TIP630
TIP630-SW-65 Windows XP/XPE/2000 Software Support for TIP630
TIP630-SW-95 QNX 6 Software Support for TIP630

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顏永富 分機35 johnny@bentech-taiwan.com

上次更新日期: 2016年04月13日。