FPGA

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TCP630 Reconfigurable FPGA with TTL/Differential I/O to PIM Module Slot 
 
Standard 3U 32 bit CompactPCI module conforming to PICMG 2.0 R3.0; User configurable Xilinx FPGA; Flash device in-system programmable; 32 bit PCI target interface by PLX PCI9030; FPGA clock options: Local clock oscillator / PLL programmable clock generator (200 KHz - 166 MHz), 6 clock outputs connected to FPGA; I/O lines: 64 TTL I/O or 32 differential I/O or 32 TTL I/O and 16 differential I/O ; TTL signaling voltage (maximum current: +/-24 mA) or EIA-422/-485 signaling level / direction individually programmable; I/O access: 64 I/O lines via a PIM Module, parallel to up to 64 I/O lines on rear connector J2; Operating temperature: -40°C to +85°C
 TCP630 Data Sheet
 TCP630-DOC User Manual for TCP630
 TDRV004-SW-42 VxWorks Software Support
 TDRV004-SW-65 Windows XP/XPE/2000 Software Support
 TDRV004-SW-72 LynxOS Software Support
 TDRV004-SW-82 LiNUX Software Support
 TDRV004-SW-95 QNX 6 Software Support

 

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TCP631 Reconfigurable FPGA with direct Connect to PIM Module Slot 
 
32 bit PCI bus mastering interface by PLX PCI9056 connected to user configurable Xilinx XC3S1500-4 Spartan-III or XC3S5000-4 Spartan-III; FPGA development tool: Free Xilinx ISE WebPack; FPGA configuration by in system programmable FlashProm via PCI bus; FPGA clock options: Local clock oscillator / PLL programmable clock generator (5 KHz - 200 MHz); 2x 128 Mbytes DDR2 RAM; I/O access: 64 ESD protected I/O lines via PIM Module slot allowing flexible I/O solutions; PCI I/O signaling voltage 3.3V and 5V; Operating temperature: -40°C to +85°C
 TCP631 Data Sheet
 TCP631-DOC User Manual for TCP631
 TDRV014-SW-65 Windows XP/XPE/2000 Software Support
 TDRV014-SW-82 LiNUX Software Support

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 02-2695-6755, 02-2695-7011, 02-2695-7033

公司傳真:+886-2-26958911

顏永富 分機35 johnny@bentech-taiwan.com

上次更新日期: 2016年04月13日。